The present invention relates to a serial peripheral interface for use in microcontroller-based products. More particularly, the present invention relates to a method and device for providing a high data rate serial peripheral interface using virtual special function registers and direct memory access techniques.
The demand for higher performance, microcontroller-based products for use in communication and processing applications continues to increase rapidly. As a result, manufacturers are requiring the components and devices within these microcontroller-based products to be continually improved to meet the design requirements of a myriad of emerging audio, video and imaging applications.
These microcontroller-based products use various types of processors, for example, general purpose microprocessors for controlling the logic of various digital devices, such as clock radios, microwave ovens, digital video recorders and the like, and special purpose microprocessors, such as math coprocessors for mathematical computations, or digital signal processors used in manipulating various types of information, including sound, imaging and video information. For the transmitting and receiving of data between various devices and components, microprocessors and other devices utilize various types of serial interfaces. One such type of interface definition typically used is the serial peripheral interface (SPI). In addition, for the temporary storage of data, for example, to permit the microprocessors to manipulate the data before transferring the data through the SPI to another device, the microprocessors generally utilize one or more buffers. These buffers are configured with the SPI""s to enable the processors to transmit and receive data to and from the buffers as needed in an application.
In many SPI applications, due to the burst nature of the data communications and the limited hardware resources available, e.g., resulting from the high costs for dedicated transfer/receive buffers and control logic, the data to be transferred or received needs to be stored in the memory devices. Such approaches thus require undesirable amounts of overhead.
Upon operation of the SPI, the CPU communicates with the memory devices for data exchange, which may be achieved by firmware controls and the like. However, when the data rate is of a prime concern, this technique dramatically affects the microcontroller operation, resulting in undesirable performance.
For example, an SPI may provide for a data structure that organizes the memory in a circular FIFO buffer configuration having various pointers, such as a CPU transmit buffer write location, a CPU receive buffer write location, an SPI transmit shift operation location, and an SPI receive shift operation location. As a result, to maintain SPI operations, a significant number of clock cycles must be available. For example, to maintain the above pointers, at least 100 clock cycles are necessary. To handle any interrupt requests for each SPI transmit/receive interrupt, at least 150 clock cycles are required. Further, to maintain the circular buffer structure, including the circular buffer head/tail wrap around, at least 30 more clock cycles are necessary. Finally, any data move instructions either to or from the memory devices would require approximately 30 or more clock cycles. As a result, over 300 clock cycles are required. Based on a clock rate of 4 MHz, the translates into a data rate of only 13 Kbytes per second, an undesirably low data rate.
Accordingly, a need exists for an improved, high performance scheme for a serial peripheral interface to provide a data rate which does not require high overhead.
The serial peripheral interface and high performance data transmission and receiving scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, an improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. In accordance with an exemplary embodiment, an exemplary technique utilizes a CPU and an SPI having a circular FIFO structure, configured with a single port memory device. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory.
In accordance with an exemplary embodiment, during a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware. In addition, once an SPI transmit/receive request is made, data communication can be established between the transmit/receive buffer and the memory. To avoid structural hazard, the transmit/receive request can be suitably pipelined until the next available clock phase, for example, within one instruction cycle. As a result, for a 4 Mhz clock rate, the technique can enable a significantly higher data transfer rate, e.g., at 250 Kbytes per second, an improvement of almost twenty times the prior art data rates.
In accordance with another aspect of the present invention, the high performance technique avoids the firmware overhead with minimum hardware control cost. For example, compared to the hardware approach using deeper buffer structures, e.g., with FIFO buffers implemented using flip-flop devices, the exemplary techniques utilize memory, e.g., dynamic or static random access memory (DRAM or SRAM) with direct memory access (DMA).